1. Field of the Invention
The present invention relates generally to methods of manufacturing MISFETs having a stacked structure of a semiconductor, an insulator, and a metal and, more particularly, to a method of manufacturing a semiconductor device including a MISFET formed on a semiconductor substrate having an SOI (Silicon-on-Insulator) structure.
2. Description of the Related Arts
With the greater integration and greater performance achieved lately in LSI technology, further miniaturization of MISFETs (metal-insulator-semiconductor field effect transistors) has been progressed. As a result, gate length is scaled to make more conspicuous the problem of a short channel effect that involves a reduced threshold voltage Vth. The short channel effect is attributable to the fact that expansion of a depletion layer in source and drain portions of the MISFET also affects a channel portion as a result of a channel length being miniaturized. One possible approach to suppress this effect is to suppress the expansion of the depletion layer in the source and drain portions by making higher impurity concentration of the channel portion. Making higher the impurity concentration of the channel portion, however, poses a problem of a deteriorated drive current caused by carrier mobility as a result of increased impurity scattering. In addition, the higher impurity concentration increases parasitic capacitance between a substrate and source or drain, thus impeding high-speed operations of the MISFET.
Conventionally, the threshold voltage Vth of the MISFET has been controlled by the impurity concentration of a channel region. The channel impurity concentration control is relatively favorably performed by making full use of ion implantation and rapid heat treatment techniques for LSIs with a design rule of about 100-hm node.
In MISFETs with 100-nm node or subsequent one, however, the technique controlling the threshold voltage Vth by impurities in the channel involves a smaller absolute number of impurities contributing to the threshold voltage Vth per MISFET with shorter channel lengths. Therefore, variations in the threshold voltage Vth caused by statistical fluctuations can no longer be disregarded (see, for example, T. Mizuno et al., “Performance Fluctuations of 0.10 μm MOSFETs—Limitation of 0.1 μm ULSIs,” Symp. on VLSI Technology 1994). There is therefore a need for a process responding to micro-devices that is capable of controlling the threshold voltage Vth of the MISFET by using also a work function of a gate electrode through the impurity concentration control for the channel portion and other methods.
To solve the foregoing problem, an SOI structure are lately gaining attention. The SOI structure uses an insulating film (e.g., an oxide silicon film) to provide complete isolation between devices. This not only suppresses soft error and latch-up and achieves greater reliability even in LSIs with greater integration, but also reduces junction capacitance of a diffusion layer. As a result, discharge/recharge from switching is reduced and the structure is advantageous in terms also of high-speed and lower power consumption applications.
The SOI type MISFET is broadly classified into two operating modes. One is a full depletion SOI, in which a depletion layer induced in a body region immediately below the gate electrode reaches a bottom surface of the body region, specifically, an interface with an embedded oxide film. The other is a partial depletion SOI, in which the depletion layer does not reach the bottom surface of the body region, leaving a neutral region.
With the full depletion SOI-MISFET, the thickness of the depletion layer immediately below the gate is limited by the embedded oxide film. There is then a substantial decrease in a depletion charge amount as compared with the partial depletion SOI-MISFET, while, instead, there is an increase in movable charge contributing to a drain current. As a result, advantageously, precipitous subthreshold characteristics (S characteristics) can be obtained.
Specifically, given the precipitous S characteristics, the threshold voltage Vth can be decreased while suppressing an offleak current. As a result, the drain current is obtained even with a low operating voltage, which makes it possible to make a MISFET that operates on, for example, 1 V or less (and a threshold voltage Vth of 0.3 V or less), thus consuming an extremely low power.
A MISFET made on an ordinary substrate has the aforementioned problem of short channel effect; however, with the full depletion SOI-MISFET, the substrate and the device are separated by the oxide film and the depletion layer does not expand, allowing substrate concentration to be lowered. As a result, reduction in the carrier mobility as a result of the increased impurity scattering can be suppressed, making for a higher drive current. In addition, in contrast to the method of controlling the threshold voltage Vth using the impurity concentration, variations in the threshold voltage Vth caused by statistical fluctuations in the number of impurities relative to a single MISFET can be reduced.
Another known art relating to the SOI-MISFET is a double gate MISFET structure as proposed, for example, in JP-A-2000-208770. In this SOI-MISFET, a source diffusion layer and a drain diffusion layer are formed with a dummy gate electrode in a SOI layer in a self-aligning manner. An inverted pattern trench of the dummy gate electrode is then formed and an embedded gate is next formed by ion implantation of impurities in a support substrate from the trench. A W or other metal film is thereafter selectively embedded in the trench region to thereby produce an upper gate electrode. Realizing the double gate structure should indeed be an effective means for enhancing SOI-MISFET performance; however, it is extremely difficult to embed and form a high concentration diffusion layer or the like in the support substrate without adversely affecting the SOI layer in the double gate MISFET structure based on the currently well-known technique. The double gate MISFET structure is therefore yet to find its practical applications. When considering an essential concept of the double gate MISFET structure, while leaving its manufacturing difficult out of consideration, accurate positioning of the embedded gate relative to the upper gate is a prerequisite and it is inevitably required that the embedded gate be disposed for each individual device. There is basically no such concept of a function of the embedded gate electrode being shared among a plurality of MISFETs. In super-miniature SOI-MISFETs, positioning error of the embedded gate is fatal, and directly associated with variations in the parasitic capacitance and drive current.
Endeavor to make effective use of the parasitic capacitance for stabilization of dynamic operations would therefore prove to be impractical unless variations of the capacitance are substantially suppressed. Further, the threshold voltage of the double gate structure SOI-MISFET is determined only by the work function of each material of the upper gate and the embedded gate, if an SOI layer thickness component is excluded. Accordingly, it is substantially impossible to set a threshold voltage value for each MISFET. It is also assumed that the embedded gate electrode and the upper gate electrode are connected in any region other than a MISFET active region, that is, a device isolation region. It is thus essential to achieve alignment in consideration of layout of peripheral devices.
In the aforementioned full depletion SOI-MISFET manufactured using an SOI substrate having an embedded insulating layer of 50 nm or less, preferably 10 nm or less, and a thin layer of single crystal semiconductor of 20 nm or less, application of a gate potential to a well diffusion layer immediately below the SOI-MISFET results in following. Specifically, high potential application of the well potential via the thin embedded insulating film further accelerates a conductive state of the SOI-MISFET, resulting in a substantial increase in the drive current, specifically, generation of a large current. If a low gate potential is applied, the well potential follows to drop, allowing the SOI-MISFET to reach a nonconductive state quickly. More specifically, in the aforementioned operating mode, characteristics can be achieved of increasing the drive current further under the same leak current condition, thus enabling switching between conductive and nonconductive states at higher speeds. Insulation isolation of a side surface of the well diffusion layer contributes to a reduced parasitic capacitance, specifically, to a delay time constant of an applied signal. In addition, the thinner the embedded insulating film, the more effective in enhancing the effect of increasing the drive current. Ideally, film thickness condition should preferably be equivalent to that of the gate insulating film of the SOI-MISFET.
As described above, the application of the thin embedded insulating film to the SOI-MISFET permits utilization of substantial performance enhancement characteristics of the double gate structure SOI-MISFET. Further, the well diffusion layer immediately below the SOI-MISFET is formed under the gate electrode in the self-aligning manner. It is therefore possible to eliminate substantially the problem of variations in the drive current and the parasitic capacitance arising from positioning error of the embedded gate electrode which was a problem with the known double gate MISFET structure.
As described above, the SOI type MISFET has outstanding characteristics of low power consumption and high speed.